This invention relates generally to digital integrated circuits and more particularly, it relates to a modular test structure for a single chip digital exchange controller (DEC) system.
As is generally known, present functional, or logic, circuitry may be quite complex due to the advent of large scale integration (LSI) wherein a very large number of semiconductor circuits are fabricated on a single chip. When the functional circuitry are desired to be made more powerful and flexible, the greater the complexity of the resulting single chip becomes. However, with such increasing complexity comes increased cost in fabrication and in testing. The entire chip may be found to be unusable due to a single flaw in its fabrication. Therefore, it is important to verify the performance of functional circuitry during assembly and also subsequently during use on a periodic basis.
Prior art digital exchange controller (DEC) systems generally have included a variety of functional blocks in which each block contains a large number of digital circuits capable of performing different logic operations. For example, such functional blocks on the DEC system may include a data link controller block, a time slot assigner block, a line interface unit block, and a multiplexer block. Each of these functional blocks are dedicated to specific functions and require specific hardware, control signals and associated interconnections for their operation. Therefore, it can be seen that the diagnostic testing of LSI DEC system chips having complex circuitry and interconnections is a very time consuming process since there are thousands and thousands of possible operating states for the high density functional blocks.
One such common prior art method uses multiplexer test interface circuitry to route testing signals from an outside diagnostic or testing equipment to input pins/nodes of the functional blocks under test and to route logic states from output pins/nodes of the functional block to the testing equipment. However, the multiplexer test interface circuitry determines which ones of the nodes on the particular functional block are to be used as inputs and which ones of the nodes are to be used as outputs. As a result, when one of the particular functional blocks on the DEC system is desired to be replaced with a different functional block the multiplexer test interface circuitry would be required to be redesigned so as to accommodate testing of the new block.
It would therefore be desirable to provide a modular test structure for a single chip DEC system in which the various functional blocks may be changed without requiring a redesign of the multiplexer test interface circuitry. This is accomplished in the present invention by providing unique test interface logic circuitry on each functional block of the DEC system chip so that every block can be operated as a self-contained module. Further, specially-designed test generation logic circuitry is formed on a bus interface unit section and is used to select one or more of the functional blocks to be tested via a microprocessor-controlled tester. The test interface logic circuitry of the selected functional blocks under test sends data direction information to the bus interface unit section to indicate how individual data bits are to be used for inputs and outputs during tests. As a result, effective and efficient testing of the different functional blocks can be accomplished by the implementation of microprogram software in the tester rather than requiring redesign of hardware on the bus interface unit section.